1. Field of Invention
The present invention relates to the field of high-voltage devices. More particularly, the present invention relates to a method of forming gate oxide layers for high-voltage devices.
2. Description of Related Art
In an integrated circuit, high-voltage devices such as electrically programmable read-only memories (EPROM) or flash memories are often included. In general, high capacitance is often required in a high-voltage device to ensure that the device is able to operate normally despite the application of a high voltage. A method of increasing the voltage bearing capacity of a high-voltage device is to thicken the gate oxide layer of the device.
FIGS. 1A-1C are schematic, cross-sectional views showing the progression of manufacturing steps in producing gate oxide layers according to a conventional method.
First, as shown in FIG. 1A, a first poly-silicon gate 14a and a second poly-silicon gate 14b are formed over a substrate 10. Then a gate oxide layer 16a is formed on the first and the second poly-silicon gates 14a, 14b.
Next, as shown in FIG. 1B, a photoresist layer 22 is formed to cover the gate oxide layer 16a and the first silicon gate 14a. The photoresist layer 22 is formed to prevent the gate oxide layer 16a on the first silicon gate 14a from being etched during a following etching step.
In the subsequent step, as shown in FIG. 1C, the gate oxide layer 16a on the first silicon gate 14b is etched by using the photoresist layer 22 as an etching mask, and becomes a thinner gate oxide layer 16b. By removing the photoresist layer 22 and forming a poly-silicon layer (not shown) on the first and the second gate oxide layers 16a, 16b, two devices (not fully shown) with different capacitance are formed. However, the quality of the gate oxide layer 16b is deteriorated, because the etching damages the surface of the gate oxide layer 16b. Additionally, forming the thinner gate oxide layer 16b by etching does not control the thickness of the gate oxide layer 16b well enough as required.